| Preface | 6 |
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| Table of Contents | 11 |
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| Towards Co-design of HW/SW/Analog Systems | 12 |
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| Introduction | 12 |
| Related Work | 14 |
| Kahn Process Networks, Timed Data Flow, and TLM | 15 |
| Executable Specification | 17 |
| Combination of KPN and TDF | 17 |
| Modeling and Simulation of KPN and TDF with SystemC | 18 |
| Architecture Exploration | 21 |
| Architecture Mapping to Analog and HW/SW Processors | 22 |
| Estimation of Quantitative Properties by System Simulation | 26 |
| Coupling of TDF and TLM Models of Computation | 27 |
| Example | 30 |
| Conclusion | 33 |
| References | 34 |
| A Flexible Hierarchical Approach for Controlling the System-Level Design Complexity of Embedded Systems | 36 |
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| Introduction | 36 |
| Related Work | 38 |
| Computational Model | 39 |
| Hierarchical Specification Method | 40 |
| Dynamic System Behavior | 42 |
| Task Behavior | 44 |
| Generating Current Model Views | 46 |
| Results | 48 |
| Conclusion | 52 |
| References | 52 |
| Side-Channel Analysis – Mathematics Has Met Engineering | 54 |
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| Introduction | 54 |
| My Personal Relation to Side-Channel Analysis | 55 |
| Timing Attack from CARDIS 1998 | 56 |
| The Original Attack DKL+98 | 57 |
| A Closer Look on Montgomery's Multiplication Algorithm | 59 |
| The Optimised CARDIS Timing Attack | 60 |
| Stochastic Properties of Montgomery's Multiplication Algorithm: Further Consequences | 64 |
| A New Method in Power Analysis | 65 |
| The Stochastic Approach | 66 |
| The Stochastic Approach Supports Design | 70 |
| Conclusion | 71 |
| References | 71 |
| Survey of Methods to Improve Side-Channel Resistance on Partial Reconfigurable Platforms | 74 |
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| Introduction | 74 |
| Reconfigurable Hardware | 75 |
| FPGA Platform Technology | 75 |
| Terminology | 77 |
| GeneralWorkflow for Partial Reconfiguration | 79 |
| Workflow for PR in Xilinx FPGAs | 81 |
| Side-Channel Attacks | 82 |
| Countermeasures against Power Attacks | 85 |
| Masking | 85 |
| Hiding | 86 |
| Reconfigurable Technology-Based Countermeasure | 88 |
| Mutating the Data Path | 89 |
| Summary and Conclusion | 93 |
| References | 93 |
| Multicast Rekeying: Performance Evaluation | 96 |
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| Introduction | 96 |
| Rekeying Benchmark Design Concept | 97 |
| Benchmark Abstraction Model | 98 |
| Benchmark Data Flow | 99 |
| Rekeying Benchmark as a Simulation Environment | 100 |
| Cost Metrics and Group Parameters | 100 |
| Evaluation Criteria and Simulation Modes | 101 |
| Rekeying Benchmark Design | 102 |
| Request Generator | 103 |
| Algorithm Manager | 107 |
| Performance Evaluator | 110 |
| Case Study | 112 |
| Conclusion | 114 |
| References | 114 |
| Robustness Analysis of Watermark Verification Techniques for FPGA Netlist Cores | 116 |
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| Introduction | 116 |
| Related Work | 118 |
| Theoretical Watermark Model for Robustness Analysis against Attacks | 119 |
| Definitions | 122 |
| Threat Model | 124 |
| Watermark Verification Strategies for Embedded FPGAs | 126 |
| Watermark Verification Using the FPGA Bitfile | 127 |
| Lookup Table Content Extraction | 127 |
| Watermarks in Functional LUTs for Netlist Cores | 128 |
| PowerWatermarking | 131 |
| Conclusions | 136 |
| References | 136 |
| Efficient and Flexible Co-processor for Server-Based Public Key Cryptography Applications | 139 |
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| Introduction | 139 |
| Related Work | 140 |
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